Often a need arises to provide variable-frequency/amplitude voltage to a load. One commonly used method to provide a variable frequency/amplitude voltage is with a Pulse Width Modulated (PWM) Voltage Source Inverter (VSI). Positive and negative DC bus voltages are provided to a VSI and, in a three phases system, three voltage supply cables link VSI outputs to a load. Exemplary VSIs include switches which are controlled to alternately link the supply cables to the positive and negative DC buses thereby producing high frequency voltage pulses on the cables. The changing average voltages of the pulses on each cable over a period defines a fundamental low frequency alternating voltage on the cable having an amplitude and a frequency.
Amplitude of the cable voltage is controlled by adjusting the ratio of positive to negative phase portions of each high-frequency pulse. Frequency of the cable voltage is controlled by altering the period over which the average high-frequency pulses alternate from positive phase to negative phase.
A controller is linked to each of the VSI switches and provides separate control signals to the switches to control the pulses. To determine when to turn switches on and off the controller receives three modulating signals Vm and a carrier signal Vc. An exemplary carrier signal Vc and a small portion of an exemplary modulating signal Vm are illustrated in FIG. 2. Carrier signal Vc includes a saw tooth signal having a relatively high carrier frequency f.sub.c and a peak carrier amplitude V.sub.c and is generally kept constant throughout control operation. Modulating signals Vm typically include sinusoidal signals (only a portion shown in FIG. 2) having relatively lower frequencies f.sub.m and a peak amplitude V.sub.m. The controller compares the reference and carrier signals and, based on relative magnitudes, turns switches on and off in a manner well known in the controls industry. Because the reference signals are sinusoidal the resulting fundamental voltage on each cable is also, ideally, essentially sinusoidal.
In the controls art an amplitude modulation index is defined as: ##EQU1##
while a frequency modulation index is defined as: ##EQU2##
As well known in the controls industry, high frequency PWM AC voltage pulses at the VSI outputs cause PWM harmonics which are often not tolerable when provided to a passive loads. Similarly, under certain conditions, high frequency PWM AC voltage pulses will cause a dynamic load such as a three phase Y-connected motor to overheat. This is because high iron core losses and high winding resistance copper losses are associated with high-frequency PWM harmonics applied to motor terminals.
The PWM VSI line-to-neutral output voltage harmonic spectrum is determined by conventional Fourier analysis of the high frequency pulsed voltage waveforms which are provided on voltage supply cables. Line-to-neutral voltage is defined as from a line or cable to a "zero voltage" reference node between the positive and negative DC rails. The mathematics of Fourier analysis defines an equivalent voltage source representation for a pulsed waveform which is a series sum of a sinewave fundamental voltage and sinewave harmonic voltages. Thus, a PWM VSI line-to-neutral output voltage source may be viewed as a sum of a sinewave fundamental voltage at the fundamental output frequency f.sub.1 in series with all the sinewave harmonic voltages V.sub.h at associated harmonic frequencies f.sub.h which comprise the waveform as determined from the Fourier analysis.
V.sub.p is the peak amplitude of the line-to-neutral sinewave fundamental frequency voltage component referenced to the zero reference node, and is defined as: ##EQU3##
The rms fundamental line-to-line voltage (V.sub..parallel.).sub.1 is therefore: ##EQU4##
Theoretically, the harmonic voltage frequencies f.sub.h are also equally well defined for those skilled in the art and are: EQU f.sub.h =(h)f.sub.1 =(jm.sub.f.+-.k)f.sub.1 jf.sub.c.+-.kf.sub.1 Eq. 5
where j is an integer and k is an integer representing a particular sideband. Thus, the harmonic voltages f.sub.h in the inverter output voltage waveform appear as sidebands centered around the carrier switching frequency f.sub.c and its multiples (e.g., 2f.sub.c, 3f.sub.c, 4f.sub.c, etc.) This general pattern holds true for all values of m.sub.a in the range between 0 and 1.
Rms harmonic components of the inverter line-to-line output voltage (V.sub.11).sub.h can be calculated from a normalized harmonic table as well known in the art. The harmonic amplitudes are tabulated in Table 1 as a function of amplitude modulation ratio ma and assuming an odd frequency modulation index m.sub.f which is greater than 9. Only those harmonics with significant amplitudes up to j=4 (see Eq. 5) are included in Table 1.
As an example of how to calculate the values in Table 1, assume a 480 V 60 Hz sinewave system voltage is applied to a variable speed drive input having a 6 pulse diode bridge front end and a VSI output which powers a 460 V 60 Hz motor @ 52 Hz. The VSI V.sub.dc bus voltage is 1.35*480 V or 650 V.sub.dc, using conventional bridge rectifier AC/DC conversion formulas. At 52 Hz the motor requires a fundamental rms voltage component of (52 Hz/60 Hz)*460 V or 399 Vrms. The normalized fundamental component ratio is thus [(V.sub.11).sub.1 /V.sub.dc ] or [399/650 =0.612]. From Table 1, this corresponds to a modulation index ratio of m.sub.a =1. Examination of the m.sub.a =1.0 column shows that the harmonic voltages centered at the carrier frequency f.sub.c and twice the carrier frequency 2f.sub.c are the two highest harmonic voltage magnitudes which contribute to a non-sinusoidal output voltage. Specifically, from Equation 5, these particular line-to-line harmonic rms voltages exist with 126.75 Vrms @ f.sub.c +/-104 Hz and 72.5 Vrms @ 2f.sub.c +/-52 Hz.
In general Table 1 shows that f.sub.c harmonics only become dominant in the 30 Hz to 60 Hz range while the 2f.sub.c harmonics are dominant throughout the 0 to 60 Hz range.
TABLE 1 Generalized harmonics of V.sub.11 for a large and odd mf &gt; 9 [(V.sub.11).sub.h /V.sub.dc ] Tabulated as Function of m.sub.a, where (V.sub.11)h is rms Value of the Harmonic Voltages Modulation Index (m.sub.a) 0.2 0.4 0.6 0.8 1.0 Fundamental Component 0.122 0.245 0.367 0.490 0.612 (h = 1) [(V.sub.II).sub.1 /V.sub.dc ] Typical output frequency (Hz) 10 20 31 42 52 [for 460 V, 60 Hz load] [(V.sub.II).sub.h /V.sub.dc ] m.sub.f .+-. 2 0.010 0.037 0.080 0.135 0.195 m.sub.f .+-. 4 0.005 0.011 2 m.sub.f .+-. 1 0.116 0.200 0.227 0.192 0.111 2 m.sub.f .+-. 5 0.008 0.020 3 m.sub.f .+-. 2 0.027 0.085 0.124 0.108 0.038 3 m.sub.f .+-. 4 0.007 0.029 0.064 0.096 4 m.sub.f .+-. 1 0.100 0.096 0.005 0.064 0.042 4 m.sub.f .+-. 5 0.021 0.051 0.073 4 m.sub.f .+-. 7 0.010 0.030
In the linear PWM modulation mode, the peak amplitude of the sinewave fundamental frequency voltage increases proportionately with an increase in m.sub.a from 0 to 1. In the PWM over-modulation mode, the peak of the sinusoidal modulating signal exceeds the peak of the carrier signal. Thus, as a result, the quantity of PWM pulses begins to decrease and inverter output voltage increases. Unlike in the linear region, the sinewave fundamental frequency rms voltage component increases non-linearly with an increase in m.sub.a &gt;1 in the PWM over-modulation mode.
In the over-modulation region more significant sideband harmonics appear centered around the harmonic frequency f.sub.c and its multiples (e.g. 2f.sub.c, 3f.sub.c). However, the amplitudes of the dominant harmonics are not as large as in the m.sub.a &lt;1 region. For the purpose of this explanation operation in the linear mode will be assumed although a generalized harmonic voltage table similar to Table 1 could be generated which corresponds to overmodulating operation of the system.
Total harmonic distortion (THD) is a standard method of measuring the amount of harmonic distortion which occurs in a waveform. THD is defined as: ##EQU5##
where V.sub.1 is the RMS voltage at the fundamental frequency and V.sub.h is the RMS voltage at the harmonic frequency. Typically THD of an unfiltered PWM inverter output voltage is between 80% and 180% depending on operating speed. To cope with such excessive THD, the ASD industry specifies motors which will tolerate expected THD given a specific VSI. In other words motors are "inverter duty rated" such that, when linked directly to VSI outputs, the motors tolerate high THD and high frequency harmonic heating caused by unfiltered PWM output voltage pulses.
Unfortunately, in inverter duty rated motors which are supposed to be able to handle heating due to PWM harmonic distortion, unfiltered PWM output voltage pulses can cause motor winding electrical insulation failure. Thus, it is not surprising that inverter duty rated motor insulation failure is not solely related to high PWM THD. Instead, it has been found that such insulation failure is also directly related to steep fronted edges of the high-frequency square wave AC voltage pulses sent by VSIs down motor cable transmission lines to motor terminals.
For a given steep voltage pulse risetime, there is a cable length beyond which a transient voltage doubling (e.g., 2 per unit or 2 pu) of the original square wave voltage peak occurs at load terminals. This voltage doubling has been referred to as "classical transmission line effect" or "reflected wave voltage spikes". Present VSI output voltage waveforms have pulse risetime of approximately 100 nanoseconds to the DC bus voltage and as such have caused transient reflected wave voltage spikes at motor terminals for motor cable distances as short as 50 feet. As inverter-to-motor cable length is increased to 500 feet, reflected wave voltage spikes at the motor terminals have been observed to further increase to 3 to 4 pu magnitudes due to complex pulsed wave interactions between the cables and motor.
Unfiltered PWM voltage pulses applied to cables beyond 1000 ft. may have another voltage doubling effect, leading to 6 to 8 pu reflected wave voltage spikes at motor terminals. The &gt;2 pu voltage spikes occurring at high frequency repetition are similar in magnitude to lightning strike and quickly degrade motor winding insulation.
In addition to overvoltages, the steep front edges of unfiltered PWM voltage pulses can cause line-to-ground electrical noise which in turn causes electromagnetic interference with sensitive electronic equipment resulting in equipment malfunction. This noise, sometimes referred to as "common mode" noise, is caused by high dv/dt of the PWM pulse edges interacting with line-to-cable cable capacitance and inherent motor stator winding line-to-ground capacitance.
To cope with reflected wave voltage spikes the industry has come up with several solutions, each of which has one or more shortcomings. A first solution includes software which is used to control an ASD in a manner calculated to reduce 3 to 4 pu motor transient reflected wave voltage spikes down to a classical 2 pu transmission line problem for long cable distances. U.S. Pat. No. 5,671,130 (hereinafter "the '130 reference") which is entitled "Method and Apparatus for Controlling Voltage Reflections using a Motor Controller " which issued on Sep. 23, 1997 discloses how the voltage spike problem is essentially eliminated by altering output pulse spacing using a VSI PWM controller while leaving PWM pulse edges and fundamental voltage unaltered. In conjunction with inverter duty motor insulation specified for repetitive voltage spikes, the robust '130 reference solution is viable for cable lengths up to 800 feet.
A second solution includes hardware mounted at motor terminals which reduces reflected wave voltage spikes to as low as 1 pu for cable lengths less than 1000 feet. U.S. Pat. No. 5,831,410 (hereinafter "the '410 reference") entitled "Apparatus Used with AC Motors for Eliminating Line Voltage Reflections" which issued on Nov. 3, 1998 discloses how reflected wave voltage spikes are reduced with specially designed cable impedance matching hardware mounted in parallel with cable leads adjacent a motor. With cable lengths less than 1000 feet the '410 reference solution leaves PWM fundamental voltage and PWM pulse edges essentially unaltered.
A third solution includes hardware mounted at VSI output terminals which reduces transient reflected wave voltage spikes to as low as lpu for cable lengths up to 1000 feet. U.S. patent application Ser. No. 09/010,454 (hereinafter "the '454 reference") which is entitled "Apparatus For Eliminating Motor Voltage Reflections and Reducing EMI Currents" and which was filed on Jan. 21, 1996 discloses how reflected wave voltage spikes are reduced with specially designed cable impedance matching hardware mounted in series with the cable leads at ASD outputs. The '454 reference solution leaves PWM fundamental voltage essentially unaltered (e.g., 0.2% voltage drop) and slows PWM pulse edge risetime.
While each of the solutions above can essentially eliminate overvoltage problems where cable lengths are less than 1000 feet, unfortunately, where cable lengths exceed 1000 feet, these solutions and other dv/dt limiting hardware solutions are not entirely effective. For example, beyond 1,000 ft. cable length the '130 reference solution often is not effective to eliminate 3 pu and 4 pu reflected wave magnitudes. Similarly, beyond 1000 feet cable lengths with the '140 and '454 reference solutions package watts losses increase and effectiveness decreases and motor overvoltage which exceeds 1.75 pu has been observed. Thus, a different solution is required beyond 1,000 ft. cable lengths. Other dv/dt limiting hardware solutions available that slow the unfiltered PWM pulse risetime are also generally ineffective at reducing the transient reflected wave voltage spikes at the motor terminals for cable lengths beyond 1,000 ft.
In addition, only the '454 reference provides an integrated hardware solution to eliminate voltage spikes at cable lengths less than 1000 feet as well as eliminate common mode noise (i.e., the '130 and '410 references do not address the common mode noise problem).
Referring to FIG. 1a, one solution for eliminating reflected wave voltage spikes and line-to-ground common mode noise in cable lengths greater than 1000 feet is to insert a conventional low pass sinewave filter 10 between the outputs of a PWM VSI 12 and transmission cables linked to a load (i.e., a motor) 14. In FIG. 1a filter 10 includes line inductors and capacitors in parallel with load 14. Resulting low dv/dt of the fundamental sinewave output insures the peak of the sinewave filter output voltage is virtually the same at motor terminals even if cable lengths are 10,000 feet or greater. In addition, resulting low dv/dt insures line-to-ground current is limited to the low peak amplitude associated with a 60 Hz charging current. Inductors and capacitors of FIG. 1a and parasitic resistance of the low pass filter are well documented having a cutoff frequency f.sub.co determined by inductor and capacitor values and -40 dB attenuation per decade beyond the cutoff frequency f.sub.co.
To achieve sine waveform benefits, conventional low pass filter design dictates that f.sub.co be 10 times less than the switching rate f.sub.c of the VSI high-frequency pulse train so that the PWM harmonics associated with VSI output are attenuated by -40 dB. In addition, f.sub.co should be 10 times greater than the fundamental frequency to prevent phase shifts in the output voltage which cause system instability.
Although simple, the conventional low pass sinewave filter design of FIG. 1a has several disadvantages. First, to obtain low THD performance, the design of FIG. 1a requires a large output capacitor and thus large reactive current which must be supplied by the VSI at startup. The majority of VSI overload kVA capability thus circulates current in the filter while starving the current required by the load. This lack of current can result in unstable system operating conditions and load oscillations at startup with resultant shutdown of the drive system.
Second, to obtain low THD, the FIG. 1a design requires large reactive current in addition to the load current which must be supplied by the VSI. The required high current can drive the VSI into overload operation when the VSI is rated for the expected load requirements. A VSI overload self-protect feature then functions to disconnect the VSI from the load.
Third, to obtain low THD, the conventional filter design requires, in addition to the load, large reactive filter kVA at the fundamental frequency which must be supplied by the VSI. Thus, the FIG. 1 a low pass filter must use a significantly larger inverter rating for the same size load powered without a filter.
Referring to FIG. 1b, an active solution which is similar to the solution of FIG. 1a compensates for loss of load current which circulates in the filter capacitors. In addition to the inductors and capacitors of filter 10 (see FIG. 1a) solution 1b includes current sensors 16, 18 placed in two of the three filter capacitor branches and sensors 20, 22 on two of the cables which actively feed current information back to a PWM controller 24 to adjust VSI output current to a magnitude equal to the combined load/filter current component. In this manner the load oscillation disadvantage is minimized. However, since the basic filter design is similar to the design of FIG. 1a, the FIG. 1b design and FIG. 1a design share the second and third disadvantages described above.
Therefore, it would be advantageous to have an apparatus which, based on application specific THD, reduces THD and reflected voltage spikes to application acceptable levels without requiring excessive filter currents which starve a load and which essentially eliminates reflected wave voltage spikes in all cable lengths without requiring large and expensive components.